1. Field of the Invention
The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit and, more particularly, a method of estimating power consumption and noise levels of an integrated circuit taking into consideration the signal waveform, the signal probability and the signal correlation on the respective signal lines within an integrated circuit.
2. Description of the Related Art
It becomes possible to manufacture very large scale integrated circuits with the advent of micromachining techniques for LSI circuits. However, the miniaturization of the circuits and the increase in the scale of integration results in the increase in noise level and the increase in power consumption. If the noise level increases, it takes much time to solve the noise problem, rendering the LSI relatively expensive. Also, if the power consumption is increased, the battery provided for an electric appliance is quickly used up for a shorter time while it becomes necessary to provide an expensive heat dissipation package. Accordingly, at the initial stages of a designing procedure, it becomes necessary to estimate the noise level and the electric power as consumed.
The circuit operation inside of the LSI chip has to be investigated for the purpose of estimating the noise level and the electric power as consumed. This is because noise and power consumption ensues from the operation of circuits, i.e., motion of electric charge. One of conventional techniques most usually employed and available for investigating the operation of circuits is the simulation of the operation by the use of test vectors, i.e., tracing the circuit operation in time series by means of a computer.
For example, most of commercial tools for evaluating the operation of circuits such as VerilogXL, PowerMill and HSPICE have been implemented with this technique. The advantages of the simulation of the operation include high precisions. On the other hand, however, it has a disadvantage of a longer processing time to complete the simulation of the operation. The increase in the scale of integration will require a furthermore longer processing time and therefore the technique making use of the simulation of the operation can not be used for future circuits.
Several techniques implemented on the basis of probability simulation are available as alternatives to the simulation of the operation. Generally speaking, the processing time of a technique implemented on the basis of probability simulation is substantially shorter than that of a technique implemented on the basis of the simulation of the operation. For this reason, the technique implemented on the basis of probability simulation is recognized as a promising technique in the future applicable for very large scale integrated circuits. However, the probability simulation is inferior to the simulation of the operation with respect to the accuracy of the evaluation. Because of this, it is the important point for the technique implemented on the basis of probability simulation to improve the accuracy without increasing the processing time. In the followings, two types of the technique implemented on the basis of probability simulation will be explained, i.e.,                (1) CREST (CuRent ESTtimator)        (2) BAM (Boolean Approximation Method).        
CREST has been published in the paper, F. N. Najm, et.al “Probabilistic Simulation for Reliability Analysis of COMS VLSI Circuits”, IEEE Transactions on Computer Aided Design, vol. 9, no. 4, pp. 439–450,1990.
The characteristics of CREST is the use of probability waveforms which have been statistically synthesized with a plurality of test vectors. FIG. 1 is a schematic diagram showing an exemplary probability waveform. There are illustrated four test vectors at the left side of a block arrow and a probability waveform as synthesized from these test vectors at the left side of the block arrow. Numerals located above the probability waveform includes numerals in squares indicative of the probabilities that the logic value changes from 0 to 1 at the respective time points, and other numerals indicative of the probabilities that the logic values 1 occur at the respective time points. The processing time of CREST is one thousandth of that of the simulation of the operation (HSPICE). However, since it is difficult to take into consideration the spatial correlation signal, the accuracy of CREST is not improved up to the accuracy of the simulation of the operation.
On the other hand, BAM is a technique taking into consideration the spatial signal correlation as described in U.S. Pat. No. 5,847,966. A typical example of the spatial signal correlation is originating from branch and convergence of a signal. In FIG. 2, there are two paths of a signal to reach the node Z from the node A as A→D→Z and A→E→Z. In such a case, a signal at the node D and a signal at the node E are depending upon the same signal at the node A and therefore they are not indpendent to each other. The correlation between the signal at the node D and the signal at the node E is reflected to the operation of the signal at the node Z and the accuracy of estimation of the noise level and the power consumption. In accordance with BAM, the accuracy is improved by taking into consideration the first order influence of the signal correlation. However, since the signal waveform is not considered in the case of BAM, it is not appropriate to make use of BAM for the purpose of analyzing the noise and the power consumption originating from the signal waveform such as a glitch and so forth (malfunction due to the differential arrival times of relevant signals).
The respective features are summarized in the following Table 1
TABLE 1PROCESSINGACCURACY OFSIGNALSIGNALSIMULATION TYPETIMEESTIMATIONWAVEFORMCORRELATIONOPERATIONLONGHIGHCONSIDEREDCONSIDEREDPROBABILITYCRESTSHORTREL. LOWCONSIDEREDNOT CONSIDEREDBAMSHORTREL. LOWNOT CONSIDEREDCONSIDEREDAs described above, the technique making use of the simulation of the operation can not be used for future circuits because of the longer processing time. On the other hand, while the technique making use of the probability simulation such as CREST, BAM has the advantage that the processing time is short, the accuracy of estimation thereof is not sufficient. Accordingly, there are demands for an appropriate technique taking into consideration both the signal waveform and the signal correlation.
It becomes furthermore increasingly important to consider the signal waveform and the signal correlation at the same time while the miniaturization of circuits has been advanced. One of the reasons thereof is the increase in the ratio of the capacitance between adjacent lines to the entire capacitance driven by signals within the circuit under consideration. By virtue of the capacitance between adjacent lines, the operation of a signal is affected by the operation of another signal. This means that the correlation between different signals must be taken into consideration. The influence of the capacitance between adjacent lines depends upon the interval between the switching times of the signals which are affected each other. This means that signal waveforms must be taken into consideration.